Semiconductor chip manufacturing requires defect analysis to help improve chip yield and monitor the production environment. Semiconductor chips are tested for the presence of physical defects at various processing steps during the manufacturing process. “In-line” measurements occur while the semiconductor chips are within the fabrication facility. Example physical defects include pinholes, voids, spikes, or agglomerations. With the aid of defect data analysis, equipment failure or fabrication facility contamination may be inferred.
Electrical measurements may be taken and further analysis performed after completing manufacture of the semiconductor chip. The electrical measurements, which produce electrical test data, or “electrical data” for short, and analysis may help improve chip yield and provide information in support of monitoring the production environment. The electrical data and analysis also support monitoring of device and circuit-level functional characteristics. Poor device or circuit-level functional characteristics may be caused by physical defects. However, physical defects may be difficult to detect after manufacture of the chip is complete.
Correlation of physical defects with electrical data may be performed through failure analysis of a limited sample size of failing chips. However, failure analysis techniques may be time consuming, expensive, and destructive. Semiconductor manufacturers have short production-cycle times that do not permit the frequent use of failure analysis techniques. The present invention may address one or more of these and related issues.